1. Field of the Invention
The present invention relates to the field of processors and, more particularly, to a technique for sharing the results of compare instructions between integer and floating point operations.
2. Related Application
The present invention is related to a copending patent application titled "Moderately Coupled Floating Point And Integer Units;" Ser. No. 08/563,499; filed Nov. 28, 1995 now U.S. Pat. No. 5,805,486.
3. Background of the Related Art
The use of integer and floating point units within or in conjunction with a processor is well-known in the art. The integer unit operates on numbers in a format capable of representing only integers (zero, positive or negative numbers without a fractional part). A typical integer unit is comprised of a number of registers for storing information and one or more execution units for operating on the stored information. A collection of registers that are accessed in a like fashion is called a register file. Typically, not all of the execution units in the integer unit will treat the contents of a register as an integer. For example, a shift execution unit operates on bit fields. Apart from the integer execution unit(s), the registers are also coupled to a bus for transfer of information to and from other units, such as memory. Thus, information can be loaded into a register of a register file from a unit such as memory, be operated on by an integer execution unit and the result stored in one of the registers, which result is typically transferred to storage elsewhere, such as in memory.
The floating point unit is configured similarly to the integer unit, but operates on numbers in a format capable of representing numbers with a fractional part. This format is incompatible with the format used to represent integer numbers. Due to the incompatible number formats, integer and floating point units typically have separate register files. The floating point format partitions a number into sign, exponent and significand (also referred to as mantissa) fields. Thus, the difference in number formats also requires a separate set of instructions for operating on integer and floating point numbers.
Processor architectures typically provide a mechanism to allow the conversion from one number format to the other, which involves the movement of data between the integer and floating point register files. For those processor architectures with separate integer and floating point register files, the processors implemented in these architectures typically have functionally separate integer and floating point units coupled to their corresponding register file. Thus, one or more integer execution units are coupled to the integer register file and one or more floating point execution units are coupled to the floating point register file. As part of the process of executing instructions, the processor routes integer instructions to the integer execution unit(s) and routes floating point instructions to the floating point execution unit(s).
The separation of the integer and floating point functions has significant advantages in performance, but has implications on conditional branch and conditional move operations in some instances. These implications generally take the form of transfers of data between the integer and floating point register files. Due to the difference between the integer register file format and the floating point register file format, these transfers may add significant overhead to certain conditional branch and conditional move operations, adversely impacting processor performance. One instance is in supplying a condition to a conditional branch (such as a conditional jump). This condition is typically generated by a compare instruction. It is useful to perform a conditional branch based on either integer or floating point data. In the case where two separate conditional branch instructions are defined in the architecture, one based on integer registers and one based on floating point registers, then the situation where a conditional branch is based on both integer and floating point data will require a data transfer due to the separation of the integer and floating point register files. In the case where the architecture defines only a single conditional branch based on integer registers, and where the floating point compare instruction is defined to write floating point registers, then the situation where a conditional branch is based on floating point data will also require the transfer of data.
Another instance is supplying a condition to a conditional move operation in which the condition is typically generated by a compare instruction. (See, for example, patent applications titled "Method For Conditionally Selecting Data;" Ser. No. 08/623,960; filed Mar. 29, 1996 and "Conditional Move Using A Compare Instruction Generating A Condition Field;" Ser. No. 08/660,094; filed Jun. 6, 1996).
It is useful to be able to perform a conditional move of floating point data based on the result of comparing integer data. It is also useful to be able to perform a conditional move of integer data based on the result of comparing floating point data. For those architectures that define two separate conditional move operations, one based on integer registers and one based on floating point registers, the two conditional move scenarios stated above will require a transfer of data. In the case where the architecture defines only a single conditional move based on integer registers and where the floating point compare instruction is defined to write floating point registers, then data transfer will be required for the case of conditionally moving floating point data based on the result of comparing integer data. Lastly, in an architecture that defines only a single conditional move based on integer registers and where the floating point compare instruction is defined to write integer registers, a conditional move of floating point data based on the result of comparing either integer or floating point data will require a transfer of data.
It is appreciated that architectural definitions other than those mentioned above are possible. For example, an architecture could be defined to have a single register file for storing both integer and floating point data rather than two separate register files. However each of these alternative architectural definitions typically has unique disadvantages in performance as compared to the architecture of the present invention.
Accordingly, the present invention describes a technique for allowing such conditional branching and conditional moving to be practiced on various combinations of integer and floating point data.